#ifndef __RISCV_ASM_H__
#define __RISCV_ASM_H__


#if __riscv_xlen == 64
#define __REG_SEL(a, b)					a
#define REG_FMT							"%016lx"
#elif __riscv_xlen == 32
#define __REG_SEL(a, b)					b
#define REG_FMT							"%08lx"
#endif

#define REG_L  __REG_SEL(ld, lw)
#define REG_S  __REG_SEL(sd, sw)


#define reg_read(reg)										\
	({                                                      \
		register unsigned long __v;                      	\
		__asm__ __volatile__("mv %0, " #reg                 \
				     : "=r"(__v)                       		\
				     :                        				\
				     : "memory");                    		\
		__v;                                             	\
	})


#define csr_read(csr)                                       \
	({                                                      \
		register unsigned long __v;                     	\
		__asm__ __volatile__("csrr %0, " #csr 				\
				     : "=r"(__v)                			\
				     :                          			\
				     : "memory");               			\
		__v;                                            	\
	})


#define csr_write(csr, val)                                 \
	({                                                      \
		register unsigned long __v = (unsigned long)(val);  \
		__asm__ __volatile__("csrw " #csr ", %0" 			\
				     :                 						\
				     : "rk"(__v)               	 			\
				     : "memory");               			\
	})

#endif
